library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.typeDefinitions.all;

entity wbInterstageReg is
  port (
    clk            : in std_logic;
    nReset         : in std_logic;
    holdStage      : in std_logic;
    invalidate     : in std_logic;
	
  
    dataMem_in        : in std_logic_vector(31 downto 0);
    destination_in : in std_logic_vector(4 downto 0);
	
 
    dataMem        	: out std_logic_vector(31 downto 0);
    destination 	: out std_logic_vector(4 downto 0));   
end wbInterstageReg;

architecture wbInterstageReg_arch of wbInterstageReg is


  signal r_dataMem, n_dataMem : std_logic_vector(31 downto 0);
  
  signal r_destination      : std_logic_vector(4 downto 0);
  signal  n_destination       : std_logic_vector(4 downto 0);

  
begin  -- fetchInterstageReg  

  destination <= r_destination;
 
 
  dataMem <= r_dataMem;


  registers : process (clk, nReset,  n_dataMem, n_destination)
  begin

    -- one register if statement
    if (nReset = '0') then
      -- Reset here      
     
      r_dataMem        <= (others => '0');	 
      r_destination <= (others => '0');                       
      
    elsif (falling_edge(clk)) then
      -- Set register here
      
   
      r_dataMem        <= n_dataMem;    
      r_destination <= n_destination;
      
    end if;
    
  end process;


  -- outputs: 
  nextState : process (holdStage, invalidate,r_dataMem, r_destination, destination_in, dataMem_in)
  begin  -- process nextState
    if(invalidate = '1') then
  
      n_dataMem        <= (others => '0');
      n_destination <= (others => '0');
      
    else
      if(holdStage = '1') then
        
        n_dataMem        <= r_dataMem;     
	
        n_destination <= r_destination;
      else
     
        n_dataMem        <= dataMem_in;      	
        n_destination <= destination_in;
      end if;
    end if;
    
    
  end process nextState;

  

end wbInterstageReg_arch;
